The present invention relates to integrated circuits and semiconductor device fabrication and, more specifically, to methods for forming self-aligned cuts and structures formed with self-aligned cuts.
A back-end-of-line (BEOL) interconnect structure may be used to connect device structures fabricated on a substrate during front-end-of-line (FEOL) processing with each other and with the environment external to the chip. Self-aligned patterning processes used to form a BEOL interconnect structure involve mandrels as sacrificial features that establish a feature pitch. Sidewall spacers, which have a smaller thickness than permitted by the current ground rules for optical lithography, are formed adjacent to the vertical sidewalls of the mandrels. After selective removal of the mandrels, the sidewall spacers are used as an etch mask to etch an underlying hardmask, for example, with a directional reactive ion etch (RIE) process. Unmasked features in the pattern are transferred from the hardmask to a dielectric layer to define trenches in which the wires of the BEOL interconnect are formed.
Cuts may be formed in mandrels with a cut mask and etching in order to section the mandrels and define gaps that subsequently are used to form adjacent wires that are spaced apart at their tips with a tip-to-tip spacing. A pattern reflecting the cut mandrels may be transferred to the hardmask and subsequently from the hardmask to the patterned dielectric layer. Non-mandrel cuts may also be formed in the hardmask itself and filled by dielectric material when the sidewall spacers are formed. These non-mandrel cuts are also transferred to the hardmask and subsequently from the hardmask to the patterned dielectric layer. The mandrel and non-mandrel cuts are filled by dielectric material of the patterned dielectric layer to fill the gaps and provide electrical isolation between the tips of the wires facing each other across the gaps.
Improved methods of forming self-aligned cuts and structures formed with self-aligned cuts are needed.